The present invention relates generally to a twin-tub complementary heterostructure field effect transistor (C-HFET) fabrication process, and more particularly to a method of fabricating complementary heterostructures field effect transistors on indium phosphide substrates.
Silicon Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been recognized as the workhorse of the modern electronic industry with Complementary MOSFET (CMOS) technology utilized for low power consumption along with high speed applications. To date, the minimum gate size has shrunk to 0.7 microns in commercial IC chips with a commensurate increase in speed and in the integration scale (too many millions of transistors on a single chip for memory ZCs).
According to Shur (M. Shur, Physics of Semiconductor Devices, 1.sup.st ed. , Prentice Hall, N.J. (1990)), the cost of a bit in a computer memory chip has dropped to about 6.times.10.sup.-3 cents/bit. Sales of MOSFET digital integrated circuits (ICs) in the United State alone have reached six billion dollars per year in the 1980s and are projected to rise; in 1986, the total IC sales in the United State were 11 billion dollars with approximately 7.5 billion dollars dedicated to CMOS ICs. It is expected that IC chips will contain up to 100 million devices per chip by the year 2000, with the cost per bit of memory below 10.sup.-4 cents.
In addition to silicon, new material systems such as GaAs and InP have emerged offering significant advantages over silicon for certain applications. Heterostructures AlGaAs/GaAs, AlGaAs/InGaAs/GaAs, and AlInAs/InGaAs/InP Field Effect Transistors (HFETs), also called Modulation Doped Field Effect Transistors (MODFETs), High Electron Mobility Transistors (HEMTs), Selectively Doped Heterojunction Transistors (SDHTs), and Two-dimensional Electron Gas Field Effect Transistors (TEGFETS), have demonstrated excellent, ultra-high-speed performance.
More recently, complementary n- and p-channel Heterostructure Insulated Gate Field Effect Transistors (HIGFETs) have been developed offering the potential for high-speed, low-power operation. In the CHFET inverter, there is very little current in both stable states, so that the power is consumed only during switching.
Both n- and p-channel devices are fabricated by using self-aligned n.sup.+ and p.sup.+ implants in the same AlGaAs/GaAs or AlInAs/InGaAs layers. This approach has been pioneered by Honeywell SRC. Other less successful approaches to fabricate Complementary HFETs have been pursued by other companies such as Rockwell Science Center, IBM Research Center, and AT&T Bell Labs, in which the complementary n- and p-devices are fabricated in selectively grown areas in the same substrate (selective regrowth approach), or in which the device materials are stacked on top of each other.
The following United State patents are of interest:
______________________________________ 4,937,474 Sitch 4,899,201 Xu et al. 4,830,980 Hsieh 4,814,851 Abrokwah et al. 4,729,000 Abrokwah 5,192,968 Schuermeyer et al. (AF Inv 19569) ______________________________________
In particular, U.S. Pat. No. 4,729,000 to Abrokwah relates to a low power complementary (Al,Ga) As/GaAs heterostructure insulated gate field effect transistor (HIGFETs) wherein a pseudomorphic InGaAs semiconductor gate is used to reduce the device threshold voltage (V.sub.T). This patent further discloses an embodiment wherein silicon was used to create the n.sup.+ implanted regions as Mg or Be have each been used to form the p implanted regions. The HIGFET utilizes two epitaxial layers grown on a semi-insulating GaAs wafer. Similar patents have disclosed to Abrokwah et al., U.S. Pat. No. 4,814,851 and to Hsieh, U.S. Pat. No. 4,830,980. The Xu et al, U.S. Pat. No. 4,899,201, relates to improved p-channel FETs and discloses a heterostructure FET formed by a narrow band gap substrate such as GaAs, InGaAs, InP, or SiGe, and a thin wide band gap layer of AlGaAs, InAlAs or Si, dependent upon the particular material used for the substrate. This patent further discloses a HIGFET which can be either a p-channel or an n-channel device depending on whether the source and drain are p.sup.+ or n.sup.+ conductivity. The Schuermeyer patent, details an approach for the fabrication of staggered complementary circuits on InP substrates. In this invention, the p-channel layer is GaAsSb while the n-channel layer is InGaAs.